Vijayvithal Jahagirdar (JVS)

Showing the uploads of JVS
Total: 2
Name MetaCPAN Author Date VCS Issues CI Licenses CT Pass CT Fail CT Unknown CT NA Coverage Dashboard Kwalitee Reverse
Verilog-VCD-Writer CPAN version for Verilog-VCD-Writer JVS 2017-12-13T03:21:45 Add repo Add repo Add repo 562 0 0 18 96.60 Add dashboard 93.75 0
SVG-Timeline-Compact CPAN version for SVG-Timeline-Compact JVS 2017-12-07T17:21:19 Add repo Add repo Add repo 590 0 0 23 82.64 Add dashboard 93.75 0

Statistics